Modern digital signal processing circuits are of central importance to recent advances in telecommunications, human/computer interface technology, image processing, and many other technologies. Analog to digital converters (ADC's) form an essential link in the signal processing pathway at the interface between the analog and digital domains. Advances in ADC technology have increased the speed, lowered the cost, and reduced the power requirements of analog to digital converters, and resulted in a proliferation of ADC applications.
Among existing ADC technologies are flash ADC, successive approximation ADC, Sigma-Delta ADC, and pipelined ADC. Flash ADC is performed by a highly parallel comparison of an input analog signal to each of a set of reference voltages. Flash ADC can provide very high speed and accuracy at the cost of high component count and high power consumption.
Successive approximation ADC uses one or a few comparators, operated iteratively, to yield high accuracy conversion with far fewer components than flash conversion. Successive approximation ADC, however, operates at much slower conversion rates than flash ADC.
Sigma-Delta converters provide high accuracy conversion by oversampling, but at conversion rates that are also significantly slower than flash conversion.
Pipeline ADC provides analog to digital conversion that, while slower than flash conversion, is faster than most other ADC architectures. Pipeline ADC's introduce a latency (delay) between analog signal input and digital signal output. Conversion throughputs of pipeline ADC's, however, approach those of flash converters. Unlike flash converters, for which component counts increase exponentially with converter resolution, the component counts of pipeline ADC converters increase linearly with resolution. Consequently, pipeline ADC converters are relatively compact, inexpensive, and power efficient. Accordingly, pipeline ADC's are widely used in portable signal processing apparatus.
Pipeline ADC's require stable, low noise, reference voltages for optimum operation. Preferably, these reference voltages are available at low cost in terms of chip real estate and power consumption.
FIG. 1 illustrates an exemplary pipeline ADC in block diagram form. The FIG. 1 circuit is shown as a single ended ADC. In common practice, however, many pipeline ADC's are implemented as fully differential circuits. Nevertheless, single ended representation has been chosen for FIG. 1 so as to reduce the complexity of the diagram, and enhance clarity of the disclosure. The exemplary converter FIG. 1 includes a 10-bit pipeline ADC such as might be integrated on a single substrate with a CMOS Active Pixel Sensor (APS) array.
The pipelined ADC 100 includes a sample-and-hold stage 102 followed by 9 conversion stages 104. Each conversion stage 104 includes a coarse ADC 106 for analog to digital conversion of a stage input signal received at a stage input 108. The coarse ADC 106 produces a 1.5 bit digital output signal at an output 110. A 1.5 bit output includes two output bits adapted to output only three possible states, rather than the four states available on a full 2 bit output. Each conversion stage 104 also includes a coarse digital to analog converter (DAC) 112 adapted to receive the 1.5 bit digital output signal of the coarse ADC 106 and produce a corresponding analog output voltage at an analog output 114. The digital output of the ADC conversion stage is also coupled to a digital correction circuit 118 having a plurality of digital inputs 120 each coupled to a respective one of the 9 conversion stages 104. Each conversion stage 104 further includes a subtracting node 122 with first 124 and second 126 analog inputs, and an analog output 128. Also included in the ADC stage 104 is a high precision gain element (amplifier) 130 with a gain of two.
Operation of the above-described conversion stage 104 is as follows: an analog stage input signal is received at an input 107 of the coarse ADC 106 and at the first (positive) input 124 of the subtracting node 122. The coarse ADC 106 produces a 1.5 bit output representing one of three possible values. This 1.5 bit output is applied to the digital input 113 of the coarse DAC 112 which, responsively, produces an analog output signal with a magnitude equal to one of three possible output signal values. As further discussed below, these three output signal values are +VR/4, 0, and −VR/4 where VR is a reference voltage of particular magnitude. The output signal of the coarse DAC is applied to the second (negative) input 126 of the subtracting node 122. The subtracting node 122 produces an output equal to an arithmetic difference between the magnitude of the analog inputs at its first and second input terminals. This difference, referred to as a residual, is then applied to an input 131 of the high-precision gain stage 130. The precision gain stage 130 produces an amplified residual output signal at its output 134 having a magnitude equal to two times the magnitude of the residual signal. This amplified residual signal is passed on to the input 108 of the next successive ADC stage 104. Meanwhile, the digital output of the coarse ADC is received by the digital correction circuit 118 and logically combined with the digital outputs of the other 8 conversion stages 104 to produce a 10 bit digital output for the pipeline ADC at the output 140 of the digital correction circuit 118.
FIG. 2 is a schematic diagram showing additional detail of the ADC conversion stage 104 described above with respect to FIG. 1. Note that as in FIG. 1, the FIG. 2 circuit is a simplified (single ended) representation of a circuit more commonly implemented as a fully differential stage. Accordingly, one sees an input terminal 108, a coarse ADC stage 106 including first 202 and second 204 comparators each having a respective first input 206 coupled to the input terminal 108 and a respective second input 208 coupled to a respective source 210, 212 of a respective reference voltage. The first 202 and second 204 comparators have respective first 214 and second 216 outputs coupled to respective first 218 and second 220 inputs of a digital latch circuit 224.
The digital latch circuit 224 includes a control input 226 and a 2 bit wide digital output 228. A coarse DAC 112 includes a multiplexer 240 with a 2-bit wide digital control input 242, first 246, second 248, and third 250 analog inputs and an analog output 252. The digital control input 242 of the DAC is coupled to the digital output 228 of the latch 224. As is well known, the analog output 252 of the multiplexer is switchingly coupled to, and assumes the electrical potential of, one of the analog inputs 246, 248, 250 depending on a signal received at the digital input 242.
The precision gain circuit 130 includes a high-gain differential amplifier 130 with a positive input 260, a negative input 262, and an output 264. The positive input 260 of the amplifier 130 is coupled to a source of constant potential (e.g. ground potential 300). The negative input 262 of the amplifier is coupled to a first plate 270 of a first capacitor 272, and a second plate of a second capacitor 276. The negative input 262 of the amplifier is also switchingly coupled to source of ground potential 300 by means of a switching device 280. The first capacitor 272 has a third plate 282 switchingly alternately coupled to the output 264 of the amplifier 130 and to the input terminal 108 of the ADC converter stage 104. The second capacitor 276 has a fourth plate 284 switchingly alternately coupled to the input terminal 108 of the ADC converter stage 104, and the analog output 252 of the multiplexer 240. The first 272 and second 276 capacitors have equal capacitance. Accordingly, the gain of the gain stage is 2 when the first capacitor 272 is switched into the feedback circuit 290.
Each conversion stage 104 of the pipeline ADC 100 requires respective sources of five electrical potentials: ground 300 (common node voltage in a fully differential system), +VR applied at input 246, −VR applied at input 250, +VR/4 210, and −VR/4 212.
FIG. 3 shows a conventional reference circuit 400 for generating the delta −Vref (=Vref_hi−Vref−lo) differential reference voltage required by a fully differential pipeline ADC. The differential reference voltage delta−Vref corresponds to the +VR and −VR reference voltages applied at the inputs 246 and 250 of the multiplexer 240 of the single-ended FIG. 2 circuit. The +Vref/4 and −Vref/4 signals required at the respective second inputs 208 of the FIG. 2 comparators 202,204 are readily derived by a capacitive voltage dividing circuit, as known in the art. The corresponding reference voltages (delta−Vref/4) required by a fully differential pipeline ADC are achieved in the same manner.
The FIG. 3 circuit includes a fixed current source 404 coupled between a source of supply voltage 406 and one end 414 of a resistive ladder 408. The current source 404 is adapted to drive a fixed current through the resistive ladder 408. The resistive ladder includes a plurality of resistors 410 with a respective plurality of tap nodes 412 disposed therebetween. A second end 416 of the resistive ladder 408 is coupled to a source of ground potential 300. A first amplifier circuit 440 having a first (positive) 442 and a second (negative) 444 input and a first output 446 is provided. Also provided is a second amplifier circuit 450 with third (positive) 452 and a fourth (negative) 454 input and a second output 456. Both amplifier circuits 440,450 are single ended.
The output 446 of the first amplifier circuit 440 is directly coupled back to the second negative input 444, yielding a gain of 1 for the first amplifier. The output 456 of the second amplifier circuit 450 is directly coupled back to the fourth negative input 454 yielding a gain of 1 for the second amplifier. The first 442 and third 452 inputs of the respective first 440 and second 450 amplifiers are coupled to respective output terminals 460, 462 of respective first 464 and second 466 switching devices. The first 464 and second 466 switching devices each has three inputs 480, each input 480 being coupled to a respective tap node 412 of the plurality of tap nodes.
When electrical current is driven through the resistive ladder 408 by the current source 404, each tap node 412 assumes a particular electrical potential. When a particular tap node 412 is switchingly coupled to the respective positive input 442,452 of the single ended amplifier 440, 450, the output 446, 456 of the amplifier assumes the voltage of the tap node. By an appropriate choice of tap nodes, a desired delta−Vref can be established between the respective outputs 446,456 of the first and second amplifiers. Because the first and second amplifiers are independent single-ended amplifiers, however, the voltage delta−Vref between the output nodes 446, 456 is subject to common mode noise. Moreover, the current that flows through the current ladder dissipates substantial power. Reference circuit 400 is thus costly in terms of thermal budget and battery resources, particularly in the context of miniature equipment.
Accordingly there is a need for a voltage reference circuit capable of supplying a stable and precise reference voltage delta−Vref to an ADC circuit such as a fully differential pipeline ADC circuit.